Function esp_idf_bindgen::rtc_clk_apll_enable

pub unsafe extern "C" fn rtc_clk_apll_enable(
    enable: bool, 
    sdm0: u32, 
    sdm1: u32, 
    sdm2: u32, 
    o_div: u32
)

@brief Enable or disable APLL

Output frequency is given by the formula: apll_freq = xtal_freq * (4 + sdm2 + sdm1/256 + sdm0/65536)/((o_div + 2) * 2)

The dividend in this expression should be in the range of 240 - 600 MHz.

In rev. 0 of ESP32, sdm0 and sdm1 are unused and always set to 0.

@param enable true to enable, false to disable @param sdm0 frequency adjustment parameter, 0..255 @param sdm1 frequency adjustment parameter, 0..255 @param sdm2 frequency adjustment parameter, 0..63 @param o_div frequency divider, 0..31