Function esp_idf_bindgen::rtc_clk_8m_enable

pub unsafe extern "C" fn rtc_clk_8m_enable(clk_8m_en: bool, d256_en: bool)

@brief Enable or disable 8 MHz internal oscillator

Output from 8 MHz internal oscillator is passed into a configurable divider, which by default divides the input clock frequency by 256. Output of the divider may be used as RTC_SLOW_CLK source. Output of the divider is referred to in register descriptions and code as 8md256 or simply d256. Divider values other than 256 may be configured, but this facility is not currently needed, so is not exposed in the code.

When 8MHz/256 divided output is not needed, the divider should be disabled to reduce power consumption.

@param clk_8m_en true to enable 8MHz generator @param d256_en true to enable /256 divider